Quote (Genthor @ May 19 2011 11:34pm)

Nekem fent van, átkonvertálhatom, ha akarod.

Quote (ecneB @ May 19 2011 09:32pm)

Tudom, hogy boldogok a lelki szegények.. Ennél mondjuk többet vártam a ventilátoros agymenésed után.

Quote (bamboo @ 19 May 2011 23:39)

nem volt kedvem válaszolni, gondoltam ennyi elég lesz, de te tovább kötekedsz. öröm látni h az embereknek mekkora pofájuk lesz az interneten.
annyira szép, h 1 post alapján megítélsz mint embert, mert egy dologba nem mélyedtem annyira bele mint te, rögtön megítélsz szar embernek, "gamestart olvasó tinédzser"-nek.
nem azt mondom h ha megismernél biztos felnéznél rám (mert nagy valószínűséggel nem), de te meg sem adod az esélyt h normálisan viszonyuljunk egymáshoz, na ez mutatja meg milyen kibaszott primitív vagy.
nyugodtan oltsál még rám amit akarsz, h te maradjál itt a kúl gyerek, legyen tiéd az utolsó szó, leszarom

Quote (bamboo @ 19 May 2011 23:39)

WALL OF TEXT

Quote (ecneB @ May 19 2011 09:41pm)

Nem belemélyedni != hülyeségeket írni. /thread




http://img507.imageshack.us/img507/2977/androl.jpg

Quote (diablo2g @ 20 May 2011 15:40)

L3-as Cache memóriáról mit tudtok? mert úgy tűnik google nem túl sokat
melyik prociban volt először? mit csinál?

Quote

A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations. As long as most memory accesses are cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory.
When the processor needs to read from or write to a location in main memory, it first checks whether a copy of that data is in the cache. If so, the processor immediately reads from or writes to the cache, which is much faster than reading from or writing to main memory.
Most modern desktop and server CPUs have at least three independent caches: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation lookaside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data. Data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.; see Multi-level caches).
....
....
....

Multi-level caches
Another issue is the fundamental tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger slower caches.
Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.
As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. For example, the Alpha 21164 (1995) had 1 to 64MB off-chip L3 cache; the IBM POWER4 (2001) had a 256[citation needed]MB L3 cache off-chip, shared among several processors; the Itanium 2 (2003) had a 6 MB unified level 3 (L3) cache on-die; the Itanium 2 (2003) MX 2 Module incorporates two Itanium2 processors along with a shared 64 MB L4 cache on a MCM that was pin compatible with a Madison processor; Intel's Xeon MP product code-named "Tulsa" (2006) features 16 MB of on-die L3 cache shared between two processor cores; the AMD Phenom II (2008) has up to 6 MB on-die unified L3 cache; and the Intel Core i7 (2008) has an 8 MB on-die unified L3 cache that is inclusive, shared by all cores. The benefits of an L3 cache depend on the application's access patterns.
Finally, at the other end of the memory hierarchy, the CPU register file itself can be considered the smallest, fastest cache in the system, with the special characteristic that it is scheduled in software—typically by a compiler, as it allocates registers to hold values retrieved from main memory. (See especially loop nest optimization.) Register files sometimes also have hierarchy: The Cray-1 (circa 1976) had 8 address "A" and 8 scalar data "S" registers that were generally usable. There was also a set of 64 address "B" and 64 scalar data "T" registers that took longer to access, but were faster than main memory. The "B" and "T" registers were provided because the Cray-1 did not have a data cache. (The Cray-1 did, however, have an instruction cache.)

Quote (ecneB @ May 20 2011 01:44pm)

wiki cpu cache hosszasan kifejti az egesz cache-s dolgot
http://en.wikipedia.org/wiki/CPU_cache

Quote (Genthor @ May 20 2011 02:05pm)

Ha valaki szakdokát akarna írni CPU-kból, akkor itt van egy oldal. Van itt minden, mi szem-szájnak ingere.

http://www.cpu-world.com/CPUs/CPU.html

Quote (diablo2g @ 20 May 2011 16:30)

ebbe se látok sok mindent l3-ról :\



ezek csak paraméterek. még életembe nem írtam igazi ( értsd: felsőoktatás-i szintű ) szakdogát, de nem hiszem hogy ez kellene bele