amd is going big with steamroller news, i kinda wanna wait for steamroller now but meh, i don't really care.
http://vr-zone.com/articles/amd-pushes-steamroller-and-excavator-forward-bullish-about-performance-increases/17088.html#Quote
We haven't included the upcoming Piledriver core (Trinity APU, Vishera CPU) in this comparison due to the fact that internally, Bulldozer and Piledriver are very similar, with the major changes being adding the support to new instructions (FMA4 is being joined by AVX 1.1, AES, F16C etc), improving IPC, reducing leakage by optimizing transistor design and offering a boost in frequency with reduced power consumption.
Comparing Steamroller to Bulldozer makes much more sense, since the two architectures are starting to differ in greater detail. First and foremost, AMD finally addressed the core starvation. Originally, Bulldozer had a single Fetch and single Decode unit, which were in charge of feeding both Integer and Float schedulers. It turns out that the size of those units were too small and quite often you'd waste precious cycles with either ALU or FPU pipelines not doing a thing. Steamroller goes back to square one and keeps the Fetch unit as a single entity, but the Decode part is now doubled. Each Decode unit feeds one INT unit (4 pipelines) and the FP Scheduler, which has three dedicated units (two 128-bit FMAC units which can act as a single 256-bit unit when you need 256-bit AVX. For legacy code, the MMX Unit is now a single separate entity (instead of multiple side half-units in Bulldozer design). Also, one of major improvements is the increase in the instruction cache size. Up until Bulldozer, AMD featured the largest L1 cache in the field - both L1 Instruction (I-Cache) and Data (D-Cache) were the same size (64KB). With 128KB of L1 cache, AMD easily compensated for the size deficit in L2 and L3 cache versus Intel Nehalem and Sandy Bridge architectures. Bulldozer sliced down L1 cache to "better than Pentium 4, but still crap", as one of our sources put it bluntly (16KB L1 D-Cache and 64KB L1 I-Cache). Steamroller increases the size of Instruction cache beyond K7/K8/K10/K10.5/BD, but L1 D-Cache won't remain the same either.
pretty much, piledriver and bulldozer aren't really a big major difference and steamroller is a big change compared to both and they admit that bulldozer was made in a rush...
i kinda now wanna just wait for steamroller instead of piledriver but meh, still unsure, i guess i could always make a piledriver rig this year and when steamroller is in the market, i could buy a decent mobo for not too much and use it for the piledriver cpu to make a htpc or something...