Verilog Questions - Topic

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Nov 6 2012 01:13pm

So i have a project (2 bit magnitude comparator) that I am currently working on and everything looks perfect except for the timing diagram for my structural module. My behavioral dataflow module came out fine on the timing diagram but my structural one looks different

Here is what it is supposed to look like:

Here is what it looks like:

Here are my Structural (left) and behavioral (right) modules

I understand that the delays will be longer on he structural timing diagram, but the values I am getting after the delays are not the same as my first, which has me confused.

This post was edited by Woodhouse on Nov 6 2012 01:23pm